Report date: Nov 6,2024
Conflict count: 361874
Publisher: Academy and Industry Research Collaboration Center
Title count: 2
Conflict count: 4


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Created: 2024-07-17 22:22:00
ConfID: 7383619
CauseID: 1638162471
OtherID: 1633750930
JT: International Journal of VLSI Design & Communication Systems
MD: Prasanth,15,1/2/3,17,2024,Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs
DOI: 10.5121/vlsic.2023.14202(Journal) (7383619-N)
DOI: 10.5121/vlsic.2024.15302(Journal)